Consider an accumulation-mode sol PMOS device with an N+ poly-gate, a channel length of a channel width of a front gate oxide of a buried oxide of a silicon thin-film of 1000A with a p-type density of 3 x 1016cm-3, and a p-type substrate doped with a density of 1015cm-3, biased at VDS = -0.01 V. (a) If the device is biased at VG2 = 2.5V and -2.5V, what is the threshold voltage? (b) At VG2 = 2.5V and -2.5V, compute CGS and plot CGS versus VG1′ (c) Analyze the CGS versus VG1 plot to find out at what VG2 the two-step phenomenon is the most noticeable. At what VG2, this two-step phenomenon disappears. (d) Compute the maximum value of the fringing capacitance. (e) If the channel length of the device is shrunk to 0.5J-tm, repeat (b). Compare the difference between considering the fringing effect and without.